1. Field of the Invention
The present invention provides an alternative current (AC) to direct current (DC) converter structure, and more particularly, provides an AC to DC converter structure with a power factor correction (PFC) capability.
2. Descriptions of the Related Art
In most AC to DC converters, the whole circuit should exhibit a pure resistive nature to an AC input voltage. For this reason, a variety of active PFC structures have been developed which, in response to an AC input voltage, may generate a corresponding AC input current.
In the design of PFC, it is essential to generate a sinusoidal current with very low total harmonic distortion (THD). Both the THD and the power factor reflect the operational performances of a PFC circuit. The power factor has a maximum value of 1, and generally in practice, a THD value is acceptable as long as it is less than 15%.
FIG. 1 shows a PFC circuit 20 with a boost-type converter topology disclosed in U.S. Pat. No. re40016. PFC circuit 20 receives an input voltage VIN, which may be a rectified AC voltage. Resistors 38 and 40 form a voltage divider configured to provide a feedback signal VINV to a terminal INV of an integrated circuit (IC) 32 by detecting a DC output voltage VO of a load capacitor 76. Capacitor 42 acts as a low-pass filter for filtering out high-frequency components of the feedback signal VINV, generating a comparison signal VCMP to a terminal CMP of IC 32. Secondary winding 39 corresponding to booster inductor 34 detects the zero-crossing of the current flowing through booster inductor 34, which is accomplished via a zero current detection (ZCD) terminal of IC 32.
In PFC circuits, the conventional ICs are configured to internally generate a sawtooth signal for comparison against the comparison signal VCMP at the CMP end to modulate the on-time of the switch. The basic idea is that when the DC output voltage VO is at a high level, the on-time of switch 36 shall be shortened to reduce the energy transferred to the output capacitor. The level of the comparison signal VCMP decreases as the output voltage VO increases. When the switch is turned on, the sawtooth signal Vsaw begins to rise. Once the rising sawtooth signal Vsaw reaching to or higher than the voltage level of the comparison signal VCMP, the switch is turned off and, accordingly, the sawtooth signal Vsaw suddenly decreases to and then remains at a minimum level without falling portion. The re-opening of the switch is triggered by purely detecting the occurrence of zero-crossing of the current flowing through the booster inductor, and the rising portion of the sawtooth signal Vsaw begins at the same time. In few successive periods of the AC input voltage VIN, the comparison signal VCMP may be considered a constant value, so the on-time of the switch also remains roughly at a constant value.
In U.S. Pat. No. re40016, the on-time of switch 36, rather than determined solely by the comparison signal VCMP, may be extended slightly to mitigate cross-over distortion as the off-time decreases “Cross-over distortion” means the THD contributed when the level of the input voltage VIN approaches the minimum point because of the insufficient voltage across booster inductor 34 to provide power. The mitigation of the cross-over distortion will lead to a decrease in the THD.
However, even if the on-time is extended slightly as the off-time decreases, the off-time may still be over short, causing unnecessary high-frequency switching loss. Besides, the variation of the on-time along with the variation of the off-time may cause an increase in the THD contrary to expectation.